參數資料
型號: X24325V-2.7
英文描述: OSC 5V SMT 7X5 CMOS PROGRM
中文描述: 先進的2線串行e的2座門鎖TM保護胎膜早破
文件頁數: 6/17頁
文件大小: 79K
代理商: X24325V-2.7
X24325
6
Figure 6. Page Write
Page Write
The X24325 is capable of a 32 byte page write opera-
tion. It is initiated in the same manner as the byte write
operation, but instead of terminating the write cycle af-
ter the first data word is transferred, the master can
transmit up to fifteen more words. After the receipt of
each word, the X24325 will respond with an acknowl-
edge.
After the receipt of each word, the five low order ad-
dress bits are internally incremented by one. The high
order bits of the word address remain constant. If the
master should transmit more than 32 words prior to
generating the stop condition, the address counter will
“roll over” and the previously written data will be over-
written. As with the byte write operation, all inputs are
disabled until completion of the internal write cycle. Re-
fer to Figure 6 for the address, acknowledge and data
transfer sequence.
Acknowledge Polling
The Max Write Cycle Time can be significantly reduced
using Acknowledge Polling. To initiate Acknowledge
Polling, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle, then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
Refer to Flow 1.
Flow 1. ACK Polling Sequence
6552 ILL F09
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS AND R/W = 0
ACK
RETURNED
NEXT
OPERATION
A WRITE
ISSUE BYTE
ADDRESS
PROCEED
ISSUE STOP
NO
YES
YES
PROCEED
ISSUE STOP
NO
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24325
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
WORD ADDRESS (n)
DATA n
DATA n+1
DATA n+31
6552 ILL F10.1
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