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參數(shù)資料
| 型號(hào)： | X24C16S8-3.5 |
| 英文描述： | Serial E2PROM |
| 中文描述： | 串行E2PROM |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | X24C16S8-3.5 |
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8
X24C16
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other read modes, however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24C16 continues to out-
put data for each acknowledge received. The read
operation is terminated by the master; by not responding
with an acknowledge and by issuing a stop condition.
The data output is sequential, with the data from address
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during
one operation. At the end of the address space (address
2047), the counter “rolls over” to 0 and the X24C16
continues to output data for each acknowledge re-
ceived. Refer to Figure 9 for the address, acknowledge
and data transfer sequence.
Figure 9. Sequential Read
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C16
SLAVE
ADDRESS
A
C
K
A
C
K
DATA n+x
S
T
O
P
P
DATA n
A
C
K
DATA n+1
A
C
K
DATA n+2
3840 FHD F15
Figure 10. Typical System Configuration
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
PULL-UP
RESISTORS
SDA
SCL
VCC
3840 FHD F16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24C16S8MB-2.7 | Serial E2PROM |
| X24C16S8MB-3 | Serial E2PROM |
| X24C16S8MB-3.5 | Serial E2PROM |
| X24C16S14-3.5 | Serial E2PROM |
| X24C16S14I | Serial E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24C16S8I | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24C16S8I-2.7 | 制造商:XIC 功能描述: |
| X24C16S8I-3 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24C16S8I-3.5 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24C16S8M | 制造商:Intersil Corporation 功能描述:EEPROM SERL 16KBIT 2KX8 5V 8SOIC - Bulk |
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