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參數(shù)資料
| 型號(hào)： | X24C45SI |
| 英文描述： | Serial AUTOSTORE⑩ NOVRAM |
| 中文描述： | 串行自動(dòng)存儲(chǔ)⑩NOVRAM |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大小： | 58K |
| 代理商： | X24C45SI |
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X24C45
3
DEVICE OPERATION
The X24C45 contains an 8-bit instruction register. It is
accessed via the DI input, with data being clocked in on
the rising edge of SK. CE must be HIGH during the entire
data transfer operation.
Table 1. contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X24C45
requires the instruction to be shifted in with the MSB first.
After CE is HIGH, the X24C45 will not begin to interpret
the data stream until a logic “1” has been shifted in on DI.
Therefore, CE may be brought HIGH with SK running
and DI LOW. DI must then go HIGH to indicate the start
condition of an instruction before the X24C45 will begin
any action.
In addition, the SK clock is totally static. The user can
completely stop the clock and data shifting will be
stopped. Restarting the clock will resume shifting of
data.
RCL and
RECALL
Either a software RCL instruction or a LOW on the
RECALL
input will initiate a transfer of E
2
PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is reset
upon power-up and must be intentionally set by the user
to enable any write or store operations. Although a recall
operation is performed upon power-up, the previous
recall latch is not set by this operation.
WRDS and WREN
Internally the X24C45 contains a “write enable” latch. This
latch must be set for either writes to the RAM or store
operations to the E
2
PROM. The WREN instruction sets
the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E
2
PROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
STO
The software STO instruction will initiate a transfer of
data from RAM to E
2
PROM. In order to safeguard
against unwanted store operations, the following condi-
tions must be true:
STO instruction issued.
The internal “write enable” latch must be set
(WREN instruction issued).
The “previous recall” latch must be set (either a
software or hardware recall operation).
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
TABLE 1. INSTRUCTION SET
Instruction
Format, I
2
I
1
I
0
1XXXX000
1XXXX001
1XXXX010
1AAAA011
1XXXX100
1XXXX101
1AAAA11X
Operation
WRDS (Figure 3)
STO (Figure 3)
ENAS
WRITE (Figure 2)
WREN (Figure 3)
RCL (Figure 3)
READ (Figure 1)
Reset Write Enable Latch (Disables Writes and Stores)
Store RAM Data in E
2
PROM
Enable AUTOSTORE Feature
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables Writes and Stores)
Recall E
2
PROM Data into RAM
Read Data from RAM Address AAAA
3833 PGM T11
X = Don’t Care
A = Address
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