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參數(shù)資料
| 型號(hào)： | X24F128SE-5 |
| 英文描述： | 2-Wire SerialFlash with Block Lock TM Protection |
| 中文描述： | 2線SerialFlash區(qū)塊可鎖定的商標(biāo)保護(hù) |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 80K |
| 代理商： | X24F128SE-5 |
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X24F128
9
PROGRAM PROTECT REGISTER (PPR)
Register Program Operation
The Program Protect Register can only be modified by
programming one data byte directly to the address
FFFFh as described below.
The data byte must contain zeroes where indicated in
the procedural descriptions below; otherwise the oper-
ation will not be performed. Only one data byte is
allowed for each Register Program Operation. The
part will not acknowledge any data bytes after the first
byte is entered. The user then has to issue a stop to
initiate the nonvolatile write cycle that programs BL0,
BL1, and PPEN to the nonvolatile bits. A stop must
also be issued after volatile register program opera-
tions to put the device into Standby.
The state of the Program Protect Register can be read
by performing a random read at FFFFh at any time.
The part will reset itself after the first byte is read. The
master should supply a stop condition to be consistent
with the protocol. After the read, the address counter
contains 0000h.
Program Protect Register: PPR (ADDR = FFFF
h
)
PEL: Program Enable Latch (Volatile)
0 = PEL reset, programming disabled.
1 = PEL set, programming enabled.
RPEL: Register Program Enable Latch (Volatile)
0 = RPEL reset, programs to the Program Protect
Register disabled.
1 = RPEL set, programs to the Program Protect
Register enabled.
BL0, BL1: Block Lock Protect Bits (Nonvolatile)
The Block Lock Protect Bits, BL0 and BL1, determine
which blocks of the array are protected. A program to a
protected block of memory is ignored, but will receive
an acknowledge. The master must issue a stop to put
the part into standby, just as it would for a valid
program; but the stop will not initiate an internal
nonvolatile write cycle. See figure 10.
PPEN: Program Protect Enable Bit (Nonvolatile)
The Program Protect (PP) pin and the Program
Protect Enable (PPEN) bit in the Program Protect
Register
control
the
Programmable
Program Protection feature. Hardware Program
Protection is enabled when the PP pin is HIGH and the
PPEN bit is HIGH, and disabled when either the PP
pin is LOW or the PPEN bit is LOW. When the chip is
Hardware Program Protected, nonvolatile writes are
disabled to the Program Protect Register, including the
Block Lock Protect bits and the PPEN bit itself, as well
as to the Block Lock protected sections in the memory
array. Only the sections of the memory array that are
not Block Lock protected, and the volatile bits PEL and
RPEL, can be programmed.
Hardware
In Circuit Programmable ROM Mode
Note that since the PPEN bit is program protected, it
cannot be changed back to a LOW state; so program
protection is enabled as long as the PP pin is held
HIGH. Thus an In Circuit Programmable ROM function
can be implemented by hardwiring the PP pin to Vcc,
programming and Block Locking the desired portion of
the array to be ROM, and then programming the
PPEN bit HIGH. Figure 11 defines the program protect
status for each combination of PPEN and PP.
Programming the PEL and RPEL bits
PEL and RPEL are volatile latches that power up in
the LOW (disabled) state. While the PEL bit is LOW,
program operations to any address other than FFFFh
will be ignored (no acknowledge will be issued after
the data byte). The PEL bit is set by programming
00000010 to address FFFFh. Once set, PEL remains
HIGH until either it is reset to 0 (by programming
00000000 to FFFFh) or until power cycles. Program-
ming PEL and RPEL does not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.
The RPEL bit controls programming to the Block Lock
Protect bits, BL0 and BL1, and the PPEN bit. If RPEL
is 0 then no programming operations can be
performed on BL0, BL1, or PPEN. RPEL is reset when
power cycles or after any nonvolatile write, including
those to the Block Lock Protect bits, the PPEN bit, or
any sector in the memory array. RPEL must be reset
before PEL can be reset. RPEL and PEL cannot be
reset in one program operation. RPEL can also be
reset by programming u00xy010 to FFFFh ONLY
when the PPR is NOT protected. This is the same
operation as in step 3 described below, and will result
in programming BL0, BL1, and PPEN.
7
6
5
4
3
2
1
0
PPEN
0
0
BL1
BL0
RPEL
PEL
0
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