X25020
Characteristics subject to change without notice.
3 of 13
REV 1.1 7/12/00
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edge of SCK.
When reading from the EEPROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25020, followed by
the 8-bit address. After the read opcode and address
are sent, the data stored in the memory at the selected
Write Enable Latch
The X25020 contains a “write enable” latch. This latch
must be SET before a write operation will be com-
pleted internally. The WREN instruction will set the
latch and the WRDI instruction will reset the latch. This
latch is automatically reset upon a power-up condition
and after the completion of a byte, page, or status reg-
ister write cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
BP0 and BP1 are set by the WRSR instruction. WEL
and WIP are read-only and automatically set by other
operations.
The Write-In-Process (WIP) bit indicates whether the
X25020 is busy with a write operation. When set to a
“1”, a write is in progress, when set to a “0”, no write is
in progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status
of the “write enable” latch. When set to a “1”, the latch
is set, when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25020 is divided into four 512-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected seg-
ments. The partitioning is controlled as illustrated
below.
7
0
6
0
5
0
4
0
3
2
1
0
BP1
BP0
WEL
WIP
Status Register Bits
BP1
0
0
1
1
Array Addresses Protected
None
$C0–$FF
$80–$FF
$00–$FF
BP0
0
1
0
1
Table 1. Instruction Set
Notes:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Instruction Name Instruction Format*
WREN
WRDI
RDSR
WRSR
READ
WRITE
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the write enable latch (enable write operations)
Reset the write enable latch (disable write operations)
Read status register
Write status register
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address (1 to 32 bytes)
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
Read Sequence
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest
address is reached ($FF), the address counter rolls over
to address $00, allowing the read cycle to be continued
indefinitely. The read operation is terminated by taking
CS HIGH. Refer to the read EEPROM array operation
sequence illustrated in Figure 1.