參數(shù)資料
型號(hào): X25020VI
英文描述: SPI Serial EEPROM
中文描述: SPI串行EEPROM
文件頁(yè)數(shù): 4/13頁(yè)
文件大小: 128K
代理商: X25020VI
X25020
Characteristics subject to change without notice.
4 of 13
REV 1.1 7/12/00
www.xicor.com
FORNEWDESGNS
To read the status register CS line is first pulled LOW
to select the device, followed by the 8-bit RDSR
instruction. After the read status register opcode is
sent, the contents of the status register are shifted out
on the SO line. Figure 2 illustrates the read status reg-
ister sequence.
Write Sequence
Prior to any attempt to write data into the X25020, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25020. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
be ignored.
To write data to the EEPROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go LOW and remain
LOW for the duration of the operation. The host may
continue to write up to 16 bytes of data to the X25020.
The only restriction is that the 16 bytes must reside on
the same page. If the address counter reaches the end
of the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time, the write operation will not be completed. Refer to
Figures 4 and 5 for a detailed illustration of the write
sequences and time frames in which CS going HIGH
are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5, 6
and 7 must be “0”. Figure 6 illustrates this sequence.
While the write is in progress following a status register
or EEPROM write sequence, the status register may
be read to check the WIP bit. During this time the WIP
bit will be HIGH.
Hold Operation
The HOLD input should be HIGH (at V
operation. If a data transfer is to be interrupted, HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW, and SCK
must also be LOW when HOLD is released.
IH
) under normal
The HOLD input may be tied HIGH either directly to
V
CC
or tied to V
CC
through a resistor.
Operational Notes
The X25020 powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The “write enable” latch is reset upon power-up.
– A WREN instruction must be issued to set the “write
enable” latch.
– CS must come HIGH at the proper clock count in
order to start a write cycle.
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