參數(shù)資料
型號: X25057S-2.7
英文描述: 5MHz Low Power SPI Serial E 2 PROM with IDLock⑩ Memory
中文描述: 5MHz的低功耗SPI串行e的2 IDLock⑩記憶胎膜早破
文件頁數(shù): 1/16頁
文件大?。?/td> 74K
代理商: X25057S-2.7
7033-1.1 5/8/97 T1/C0/D0 SH
Xicor, Inc. 1994 – 1997 Patents Pending
1
Characteristics subject to change without notice
4K
X25057
512 x 8 Bit
5MHz Low Power SPI Serial E
2
PROM with IDLock Memory
FEATURES
5MHz Clock Rate
IDLock Memory
—IDLock First or Last Page, Any 1/4 or Lower 1/2
of E
PROM Array
Low Power CMOS
—<1
μ
A Standby Current
—<3mA Active Current during Write
—<400
μ
A Active Current during Read
1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation
Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
SPI Modes (0,0 & 1,1)
512 x 8 Bits
—16 Byte Page Mode
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
8-Lead MSOP Package
8-Lead TSSOP Package
8-Lead SOIC Package
8-Lead PDIP Package
2
DESCRIPTION
The X25057 is a CMOS 4K-bit serial E
organized as 512 x 8. The X25057 features a Serial
Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
2
PROM, internally
IDLock is a programmable locking mechanism which
allows the user to lock system ID and parametric data in
different portions of the E
ranging from as little as one page to as much as 1/2 of
the total array. The X25057 also features a WP pin that
can be used for hardwire protection of the part, disabling
all write attempts, as well as a Write Enable Latch that
must be set before a write operation can be initiated.
2
PROM memory space,
The X25057 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
TM
FUNCTIONAL DIAGRAM
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE CONTROL LOGIC
DATA REGISTER
Y DECODE LOGIC
X
DECODE
LOGIC
HIGH VOLTAGE
CONTROL
4K E
2
PROM
ARRAY
(512 x 8)
SO
SI
SCK
CS
WP
8
16
32
7033 FRM F01
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