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參數(shù)資料
| 型號： | X25097VI-1.8 |
| 英文描述： | 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory |
| 中文描述： | 5MHz的低功耗SPI串行e的2 IDLock商標(biāo)記憶胎膜早破 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 71K |
| 代理商： | X25097VI-1.8 |
X25097
4
IDLock Operation
Prior to any attempt to perform an IDLock Operation, the
WREN instruction must first be issued. This instruction
sets the “Write Enable” latch and allows the part to
respond to an IDLock sequence (Figure 7). The IDLock
instruction follows and consists of one command byte fol-
lowed by one IDLock byte (See Figure 1). This byte con-
tains the IDLock bits IDL2-IDL0. The rest of the bits [7:3]
are unused and must be written as zeroes. Bringing CS
HIGH after the two byte IDLock instruction initiates a
nonvolatile write to the Status Register. Writing more
than one byte to the Status Register will overwrite the
previously written IDLock byte. See Table 1.
Operational Notes
The X25097 powers up in the following state:
The device is in the low power, standby state.
A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
SO pin is at high impedance.
The “Write Enable” latch is reset.
Data Protection
The following circuitry has been included to prevent inad-
vertant writes:
The “Write Enable” latch is reset upon power-up.
A WREN instruction must be issued to set the “Write
Enable” latch.
CS must come HIGH at the proper clock count in order
to start a write cycle.
Table 1. Instruction Set and Block Lock Protection Byte Definition
7038 FRM T03
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
Instruction Format*
Instruction Name and Operation
0000 0110
WREN: Set the Write Enable Latch (Write Enable Operation)
0000 0100
WRDI: Reset the Write Enable Latch (Write Disable Operation)
0000 0001
IDLock Instruction—followed by:
IDLock Byte: (See Figure 1)
0000 0000 --->NO IDLock: 00h-00h- - - - - - - - - - ->None of the Array
0000 0001 --->IDLock Q1: 0000h-00FFh - - - - - - ->Lower Quadrant (Q1)
0000 0010 --->IDLock Q2: 0100h-01FFh - - - - - - ->Q2
0000 0011 --->IDLock Q3: 0200h-02FFh - - - - - - ->Q3
0000 0100 --->IDLock Q4: 0300h-03FFh - - - - - - ->Upper Quadrant (Q4)
0000 0101 --->IDLock H1: 0000h-01FFh - - - - - - ->Lower Half of the Array (H1)
0000 0110 --->IDLock P0: 0000h-000Fh - - - - - - ->Lower Page (P0)
0000 0111 --->IDLock Pn: 03F0h-03FFh - - - - - - ->Upper Page (Pn)
0000 0101
READ STATUS: Reads IDLock & write in progress status on SO Pin
0000 0010
WRITE: Write operation followed by address and data
0000 0011
READ: Read operation followed by address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X25097VI-2.7 | 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory |
| X25097 | 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory |
| X25097P | 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory |
| X25097P-2.7 | 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory |
| X25097PI | 5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X25097VI-2.7 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:5MHz Low Power SPI Serial E 2 PROM with IDLock TM Memory |
| X25097VIG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:5MHz Low Power SPI Serial E2PROM with IDLockTM Memory |
| X25097VIG-1.8 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:5MHz Low Power SPI Serial E2PROM with IDLockTM Memory |
| X25097VIG-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:5MHz Low Power SPI Serial E2PROM with IDLockTM Memory |
| X251 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:X200 SERIES (CMOS) STANDARD SPECFITIONS |
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