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參數資料
| 型號： | X25642PM-2.7 |
| 英文描述： | CAP,Non-Specified,20uF,10-% Tol,10+% Tol |
| 中文描述： | 先進的SPI串行E與商標保護鎖座2胎膜早破 |
| 文件頁數： | 1/16頁 |
| 文件大?。?/td> | 76K |
| 代理商： | X25642PM-2.7 |
Advanced SPI Serial E
2
PROM with Block Lock
TM
Protection
64K
8K x 8 Bit
3132-1.0 1/17/97 T5/C0/D1 SH
Xicor, Inc. 1994, 1995, 1996 Patents Pending
1
Characteristics subject to change without notice
X25642
FEATURES
2MHz Clock Rate
Low Power CMOS
—
<1
μ
A Standby Current
—<5mA Active Current
2.7V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
8K X 8 Bits
—32 Byte Page Mode
Block Lock Protection
—
Protect 1/4, 1/2 or all of E
Built-in Inadvertent Write Protection
—Power-Up/Down protection circuitry
—Write Enable Latch
—Write Protect Pin
Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
High Reliability
—Endurance: 100,000 cycles
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
Packages
—8-Lead PDIP
—8-Lead SOIC
—14-Lead SOIC
—20-Lead TSSOP
2
PROM Array
DESCRIPTION
The X25642 is a CMOS 65,536-bit serial E
internally organized as 8K x 8. The X25642 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
2
PROM,
The X25642 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25642 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25642 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25642 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
TM
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
CONTROL
AND
TIMING
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
8K BYTE
ARRAY
64 X 256
Y DECODE
DATA REGISTER
SO
SI
SCK
CS
HOLD
WP
64
128
8
32
STATUS
REGISTER
64
128 X 256
64 X 256
3132 ILL F01.1
FUNCTIONAL DIAGRAM
Direct Write
and Block Lock
Protection is a trademark of Xicor, Inc.
A
PPLICATION
N
OTE
A V A I L A B L E
AN19 AN38 AN41 AN61
相關PDF資料 |
PDF描述 |
|---|---|
| X25642SI-2.7 | Advanced SPI Serial E 2 PROM with Block Lock TM Protection |
| X25642SM-2.7 | Advanced SPI Serial E 2 PROM with Block Lock TM Protection |
| X25642S8 | Advanced SPI Serial E 2 PROM with Block Lock TM Protection |
| X25642S8I | Advanced SPI Serial E 2 PROM with Block Lock TM Protection |
| X25642S8I-2.7 | Advanced SPI Serial E 2 PROM with Block Lock TM Protection |
相關代理商/技術參數 |
參數描述 |
|---|---|
| X25642PMG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced SPI Serial E2PROM with Block Lock Protection |
| X25642PMG-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced SPI Serial E2PROM with Block Lock Protection |
| X25642S | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Advanced SPI Serial E 2 PROM with Block Lock TM Protection |
| X25642S-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced SPI Serial E2PROM with Block Lock Protection |
| X25642S8 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced SPI Serial E2PROM with Block Lock Protection |
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