參數(shù)資料
型號(hào): X28C256JI-25
英文描述: 5 Volt, Byte Alterable E2PROM
中文描述: 5伏,可變E2PROM的字節(jié)
文件頁數(shù): 2/24頁
文件大?。?/td> 113K
代理商: X28C256JI-25
2
X28C256
PIN DESCRIPTIONS
Addresses (A
0
–A
14
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (
CE
)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (
OE
)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X28C256 through the
I/O pins.
Write Enable (
WE
)
The Write Enable input controls the writing of data to the
X28C256.
PIN NAMES
Symbol
A
0
–A
14
I/O
0
–I/O
7
WE
CE
OE
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3855 PGM T01
3855 FHD F01
X BUFFERS
LATCHES AND
DECODER
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
CONTROL
LOGIC AND
TIMING
256K-BIT
E2PROM
ARRAY
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
VCC
VSS
A0–A14
ADDRESS
INPUTS
WE
FUNCTIONAL DIAGRAM
X28C256
11
I/O0
10
A0
14
VSS
9
A1
8
A2
7
A3
6
A4
5
A5
2
A12
28
VCC
12
I/O1
13
I/O2
15
I/O3
4
A6
3
A7
1
A14
16
I/O4
20
CE
22
OE
24
A9
17
I/O5
27
WE
19
I/O7
21
A10
23
A11
25
A8
18
I/O6
26
A13
BOTTOM VIEW
PGA
3855 FHD F04
PIN CONFIGURATION
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