參數(shù)資料
型號(hào): X28C256SM-25
英文描述: 5 Volt, Byte Alterable E2PROM
中文描述: 5伏,可變E2PROM的字節(jié)
文件頁(yè)數(shù): 1/24頁(yè)
文件大?。?/td> 113K
代理商: X28C256SM-25
X28C256
1
5 Volt, Byte Alterable E
2
PROM
Xicor, Inc. 1991, 1995 Patents Pending
3855-1.9 8/1/97 T1/C0/D8 EW
Characteristics subject to change without notice
DESCRIPTION
The X28C256 is an 32K x 8 E
2
PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C256 is a 5V only device. The
X28C256 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28C256 supports a 64-byte page write operation,
effectively providing a 78
μ
s/byte write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The X28C256 also features
DATA
and Toggle Bit Polling, a system software support
scheme used to indicate the early completion of a write
cycle. In addition, the X28C256 includes a user-optional
software data protection mode that further enhances
Xicor’s hardware write protect capability.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
FEATURES
Access Time: 200ns
Simple Byte and Page Write
— Single 5V Supply
—No External High Voltages or V
PP
Control
Circuits
— Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 60mA
—Standby: 200
μ
A
Software Data Protection
— Protects Data Against System Level
Inadvertent Writes
High Speed Page Write Capability
Highly Reliable Direct Write
Cell
— Endurance: 100,000 Write Cycles
— Data Retention: 100 Years
Early End of Write Detection
DATA
Polling
—Toggle Bit Polling
256K
X28C256
32K x 8 Bit
PIN CONFIGURATION
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
X28C256
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
3855 FHD F02
TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X28C256
A3
A4
A5
A6
A7
A12
A14
NC
VCC
NC
WE
A13
A8
A9
A11
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
3855 ILL F23
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4
3
2
1 32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
X28C256
A7
A1
A1
N
VC
W
A1
I1
I2
VS
N
I3
I4
I5
LCC
PLCC
3855 FHD F03
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