X28LV010
Characteristics subject to change without notice.
2 of 18
PIN CONFIGURATIONS
2
32
4 3
31
NC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE
NC
A
14
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
X28LV010
PDIP
X28LV010
(Top View)
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
A
14
A
13
A
8
A
9
A
11
I/O
7
I
1
I
2
V
S
I
3
I
4
I
5
I
6
A
1
A
1
N
V
C
W
N
6
7
1
5
8
9
10
11
12
1315
14
17
16
18 1920
22
23
24
25
26
27
28
29
OE
A
10
CE
A
7
21
30
PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
X28LV010
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
NC
V
SS
NC
NC
I/O
2
I/O
1
I/O
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
11
A
9
A
8
A
13
A
14
NC
NC
NC
WE
V
CC
NC
NC
NC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
TSOP
A
1
A
0
A
1
A
2
A
3
PIN DESCRIPTIONS
Addresses (A
The Address inputs select an 8-bit memory location
during a read or write operation.
0
–A
16
)
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers and is used to initiate read operations.
Data In/Data Out (I/O
Data is written to or read from the X28LV010 through
the I/O pins.
0
–I/O
7
)
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28LV010.
PIN NAMES
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Symbol
A
0
–A
I/O
0
–I/O
WE
CE
OE
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+3.3V
Ground
No Connect
16
7