參數(shù)資料
型號(hào): X28LV010JI-15
元件分類(lèi): EEPROM
英文描述: 128Kx8 EEPROM
中文描述: 128Kx8 EEPROM
文件頁(yè)數(shù): 5/18頁(yè)
文件大?。?/td> 141K
代理商: X28LV010JI-15
X28LV010
Characteristics subject to change without notice.
5 of 18
The Toggle Bit I/O
6
Figure 4. Toggle Bit Bus Sequence
CE
OE
WE
I/O
6
X28LV010
Ready
V
OH
V
OL
Last
Write
High Z
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeep-
ing chore of saving and fetching the last address and
data written to a device in order to implement DATA
Polling. This can be especially helpful in an array com-
prised of multiple X28LV010 memories that is fre-
quently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applica-
tions. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow dia-
gram in Figure 5 illustrates a method for polling the
Toggle Bit.
HARDWARE DATA PROTECTION
The X28LV010 provides three hardware features that
protect nonvolatile data from inadvertent writes.
– Noise Protection—A WE pulse less than 10ns will
not initiate a write cycle.
– Default V
CC
Sense—All functions are inhibited when
V
CC
is
2.5V.
– Write inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle dur-
ing power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
The X28LV010 offers a software controlled data pro-
tection feature. The X28LV010 is shipped from Xicor
with the software data protection NOT ENABLED: that
is the device will be in the standard operating mode. In
this mode data should be protected during power-up/
-down operations through the use of external circuits.
The host would then have open read and write access
of the device once V
CC
was stable.
Load ACCUM
from ADDR n
Compare
ACCUM with
ADDR n
Ready
NO
YES
Last Write
Compare
OK
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