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參數(shù)資料
| 型號： | X28LV010T-70 |
| 元件分類： | EEPROM |
| 英文描述： | 128Kx8 EEPROM |
| 中文描述： | 128Kx8 EEPROM |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 141K |
| 代理商： | X28LV010T-70 |
X28LV010
Characteristics subject to change without notice.
3 of 18
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28LV010 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 5ms.
Page Write Operation
The page write feature of the X28LV010 allows the
entire memory to be written in 2.5 seconds. Page write
allows two to two hundred fifty-six bytes of data to be
consecutively written to the X28LV010 prior to the
commencement of the internal programming cycle.
The host can fetch data from another device within the
system during a page write operation (change the
source address), but the page address (A
A
16
) for each subsequent valid write cycle to the part
during this operation must be the same as the initial
page address.
8
through
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty five
bytes in the same manner as the first byte was written.
Each successive byte load cycle, started by the WE
HIGH to LOW transition, must begin within 100μs of
the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within
100μs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100μs.
Write Operation Status Bits
The X28LV010 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
DATA Polling (I/O
The X28LV010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28LV010, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true
data. Note: If the X28LV010 is in the protected state
and an illegal write operation is attempted DATA Polling
will not operate.
7
)
7
(i.e., write
Toggle Bit (I/O
6
)
The X28LV010 also provides another method for deter-
mining when the internal write cycle is complete. Dur-
ing the internal programming cycle, I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
5
TB
DP
4
3
2
1
0
I/O
Reserved
Toggle Bit
DATA Polling
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| X28LV010T-90 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
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| X28LV010TI-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
| X28LV010TI-90 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
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