參數(shù)資料
型號: X3100Q
英文描述: WAFER(ARM)
中文描述: 電池管理
文件頁數(shù): 18/40頁
文件大?。?/td> 249K
代理商: X3100Q
X3100/X3101 – Preliminary Information
Characteristics subject to change without notice.
18 of 40
REV 1.1.8 12/10/02
www.xicor.com
Over-Current Protection
In addition to monitoring the battery cell voltages, the
X3100 and X3101 continually monitor the voltage VCS
21
(VCS
2
–VCS
1
) across the current sense resistor
(R
SENSE
). If VCS
21
> V
OC
for a time exceeding T
OC
,
then the device enters over-current protection mode
(Figure 7). In this mode, the X3100 and X3101
automatically switch the discharge FET OFF (UVP/
OCP=Vcc) and hence prevent current from flowing
through the terminals P+ and P-.
Figure 7. Over-Current Protection
The 5VDC voltage regulator output (V
RGO
) is always
active during an over-current protection mode.
Once the device enters over-current protection mode,
the X3100 and X3101 begin a load monitor state. In the
load monitor state, a small current (I
LMON
=7.5μA typ.) is
passed out of pin OVP/LMON in order to determine the
load resistance. The load resistance is the impedance
seen looking out of pin OVP/LMON, between terminal
P+ and pin VSS (See Figure 7.)
If the load resistance >
150k
(I
LMON
=0μA) for a time
exceeding T
OCR
, then the X3100 or X3101 is released
from over-current protection mode. The discharge FET
is then automatically switched ON (UVP/OCP=Vss) by
the X3100 or X3101, unless the status of UVP/OCP has
been changed in control register (by manipulating bit
UVPC) during the over-current protection mode.
T
OC
/T
OCR
are varied using a capacitor (C
OC
) connected
between pin OCT and VSS. A list of typical delay times
is shown in Table 23. Note that the value C
OC
should be
larger than 1nF.
The delay T
OC
and T
OCR
that results from a particular
capacitance C
OC
can be approximated by the following
equations:
T
OC
(ms)
10,000 x C
OC
(μF)
T
OCR
(ms)
10,000 x C
OC
(μF)
Table 23. Typical Over-Current Delay Times
The value of V
OC
can be selected from the values
shown in Table 6, by setting bits VOC1, VOC0 in the
configuration register using the WCFIG command.
Note: If the Charge FET is turned off, due to an
overcharge condition or by direct command from the
microcontroller, the cells are not in an undervoltage
condition and the pack has a load, then excessive
current may flow through Q10 and diode D1. To
eliminate this effect, the gate of Q10 can be turned off by
the microcontroller through an unused X3101 cell
balance output, or directly from a microcontroller port
instead of connecting to V
RGO
.
FET Control
Circuitry
OVP/LMON
Q2
D1
I
LMON
X3100/X3101
P+
P-
Load
VCS1
VCS2
VSS
R
SENSE
V
RGO
Q10
Symbol
Description
Over-current
detection delay
Over-current
release time
C
OC
Delay
T
OC
0.001
μ
F
10ms (Typ)
T
OCR
0.001
μ
F
10ms (Typ)
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