X3100/X3101 – Preliminary Information
Characteristics subject to change without notice.
2 of 40
REV 1.1.8 12/10/02
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PRINCIPLES OF OPERATION
The X3100 and X3101 provide two distinct levels of
functionality and battery cell protection:
First, in Normal mode, the device periodically checks
each cell for an over-charge and over-discharge state,
while continuously watching for a pack over-current
condition. A protection mode violation results from an
over-charge, over-discharge, or over-current state. The
thresholds for these states are selected by the user
through software. When one of these conditions occur, a
Discharge FET or a Charge FET or both FETs are
turned off to protect the battery pack. In an over-
discharge condition, the X3100 and X3101 devices go
into a low power sleep mode to conserve battery power.
During sleep, the voltage regulator turns off, removing
power from the microcontroller to further reduce pack
current.
Second, in Monitor mode, a microcontroller with A/D
converter measures battery cell voltage and pack current
via pin AO and the X3100 or X3101 on-board MUX. The
user can thus implement protection, charge/discharge,
cell balancing or gas gauge software algorithms to suit
the specific application and characteristics of the cells
used. While monitoring these voltages, all protection
circuits are on continuously.
In a typical application, the microcontroller is also
programmed to provide an SMBus interface along with
the Smart Battery System interface protocols. These
additions allow an X3100 or X3101 based module to
adhere to the latest industry battery pack standards.
PIN CONFIGURATION
PIN NAMES
PIN DESCRIPTIONS
Battery Cell Voltage (VCELL1-VCELL4):
These pins are used to monitor the voltage of each
battery cell internally. The voltage of an individual cell
can also be monitored externally at pin AO.
The X3100 monitors 4 battery cells. The X3101 monitors
3 battery cells. For the X3101 device connect the
VCELL4/VSS pin to ground.
VCC
RGP
RGC
RGO
UVP/OCP
VCELL1
CB1
VCELL2
CB2
1
2
3
4
28
27
26
25
28 Lead TSSOP
OVP/LMON
CS
SCK
SO
VCELL3
CB3
VCELL4/VSS*
CB4
VSS
5
6
7
8
24
23
22
21
X3100/
X3101
SI
AS2
AS1
VCS1
VCS2
OVT
UVT
OCT
9
10
11
12
13
14
20
19
18
17
16
15
AS0
AO
*For X3101, Connect to ground.
Pin
1
2
3
4
5
6
Symbol
VCELL1 Battery cell 1 voltage input
CB1
Cell balancing FET control output 1
VCELL2 Battery cell 2 voltage
CB2
Cell balancing FET control output 2
VCELL3 Battery cell 3 voltage
CB3
Cell balancing FET control output 3
VCELL4/
VSS
Ground (X3101)
CB4
Cell balancing FET control output 4
V
SS
Ground
VCS1
Current sense voltage pin 1
VCS2
Current sense voltage pin 2
OVT
Over-charge detect/release time input
UVT
Over-discharge detect/release time input
OCT
Over-current detect/release time input
AO
Analog multiplexer output
AS0
Analog output select pin 0
AS1
Analog output select pin 1
AS2
Analog output select pin 2
SI
Serial data input
SO
Serial data output
SCK
Serial data clock input
CS
Chip select input pin
OVP/
LMON
Load Monitor output
UVP/
OCP
Over-current protection output
RGO
Voltage regulator output pin
RGC
Voltage regulator control pin
RGP
Voltage regulator protection pin
V
CC
Power supply
Description
7
Battery cell 4 voltage (X3100)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Over-charge Voltage Protection output/
24
Over-discharge protection output/
25
26
27
28