參數(shù)資料
型號(hào): X40420S14-C
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述: 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝: 0.150 INCH, SOIC-14
文件頁(yè)數(shù): 14/25頁(yè)
文件大?。?/td> 156K
代理商: X40420S14-C
PRELMNARY
X40420/X40421 – Preliminary
Characteristics subject to change without notice.
14 of 25
REV 1.2.14 7/12/02
www.xicor.com
Word Address
The word address is either supplied by the master or
obtained from an internal counter.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for
t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
Figure 17. Sequential Read Sequence
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
A
C
K
A
C
K
(n is any integer greater than 1)
Data
(1)
Figure 15. Random Address Read Sequence
Figure 16. X40410/11 Addressing
0
Slave
Address
Byte
Address
A
C
A
C
S
t
a
r
t
S
t
o
p
Slave
Address
A
C
1
S
t
a
r
t
SDA Bus
Signals from
Signals from
the Master
1 0 1
0
0
General Purpose Memory
Control Register
Fault Detection Register
1
1
1
0
0
0
1
1
1
0
1
1
A8 R/W
1
0
Word Address
A7
1
1
1
Slave Byte
0
0
0
0
0
0
R/W
R/W
General Purpose Memory
Control Register
Fault Detection Register
A6
1
A5
1
1
A4
1
1
A1
1
1
A0
1
1
A3
1
1
A2
1
1
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