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參數(shù)資料
| 型號(hào)： | X40421S14-A |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Dual Voltage Monitor with Intergrated CPU Supervisor |
| 中文描述： | 雙電壓監(jiān)視器集成CPU監(jiān)控 |
| 文件頁(yè)數(shù)： | 6/25頁(yè) |
| 文件大小： | 156K |
| 代理商： | X40421S14-A |
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PRELMNARY
X40420/X40421 – Preliminary
Characteristics subject to change without notice.
6 of 25
REV 1.2.14 7/12/02
www.xicor.com
Resetting the V
TRIPx
Voltage
To reset a V
TRIPx
voltage, apply the programming voltage
(Vp) to the WDO pin before a START condition is set up
on SDA. Next, issue on the SDA pin the Slave Address
A0h followed by the Byte Address 03h for V
TRIP1
and
0Bh for V
TRIP2
, followed by 00h for the Data Byte in order
to reset V
TRIPx
. The STOP bit following a valid write oper-
ation initiates the programming sequence. Pin WDO must
then be brought LOW to complete the operation.
After being reset, the value of V
TRIPx
becomes a nominal
value of 1.7V or lesser.
Note:
This operation does not corrupt the memory array.
System Battery Switch
As long as V
CC
exceeds the low voltage detect threshold
V
TRIP
, V
OUT
is connected to V
CC
through a 5 Ohm (typi-
cal) switch. When the V
CC
has fallen below V1
TRIP
, then
V
CC
is applied to V
OUT
if V
CC
is or equal to or greater
than V
BATT
– 0.03V. When V
CC
drops to less than V
BATT
– 0.03V, then V
OUT
is connected to V
BATT
through an 80
Ohm (typical) switch. V
OUT
typically supplies the system
static RAM voltage, so the switchover circuit operates to
protect the contents of the static RAM during a power fail-
ure. Typically, when V
CC
has failed, the SRAMs go into a
lower power state and draw much less current than in
their active mode. When V
CC
returns, V
OUT
switches
back to V
CC
when V
CC
exceeds V
BATT
+ 0.03V. There is
a 60mV hysteresis around this battery switch threshold to
prevent oscillations between supplies.
While V
CC
is connected to V
OUT
the BATT-ON pin is
pulled LOW. The signal can drive an external PNP tran-
sistor to provide additional current to the external circuits
during normal operation.
Operation
The device is in normal operation with V
CC
as long as
V
CC
> V
TRIP1
. It switches to the battery backup mode
when V
CC
goes away.
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh. It
can only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation. Prior to
writing to the Control Register, the WEL and RWEL bits
must be set using a two step process, with the whole
sequence requiring 3 steps. See "Writing to the Control
Registers" on page 8.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0, and BP The X40420 will not
acknowledge any data bytes written after the first byte is
entered.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Condition
V
CC
> V
TRIP1
V
CC
> V
TRIP1
&
V
BATT
= 0
0
≤
V
CC
≤
V
TRIP1
and V
CC
< V
BATT
Mode of Operation
Normal Operation
Normal Operation without battery
backup capability
Battery Backup mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
7
6
5
4
3
0
2
1
0
PUP1 WD1
WD0
BP
RWEL WEL PUP0
Figure 5. Sample V
TRIP
Reset Circuit
1
6
2
7
14
13
9
8
X40420
V
TRIP1
Adj.
V
P
RESET
4.7K
SDA
SCL
μC
Adjust
Run
V2FAIL
V
TRIP2
Adj.
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| X40421S14-B | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40421S14-C | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40421S14I-A | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40421S14I-B | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40421S14I-C | Dual Voltage Monitor with Intergrated CPU Supervisor |
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參數(shù)描述 |
|---|---|
| X40421S14-AT1 | 功能描述:IC VOLT MON DUAL SUP/SW 14-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40421S14-B | 功能描述:IC VOLT MON DUAL SUP/SW 14-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40421S14-BT1 | 功能描述:IC VOLT MON DUAL SUP/SW 14-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40421S14-C | 功能描述:IC VOLT MON DUAL SUP/SW 14-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40421S14-CT1 | 功能描述:IC VOLT MON DUAL SUP/SW 14-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
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