參數(shù)資料
型號: X40421V14I-B
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Dual Voltage Monitor with Intergrated CPU Supervisor
中文描述: 雙電壓監(jiān)視器集成CPU監(jiān)控
文件頁數(shù): 11/25頁
文件大?。?/td> 156K
代理商: X40421V14I-B
PRELMNARY
X40420/X40421 – Preliminary
Characteristics subject to change without notice.
11 of 25
REV 1.2.14 7/12/02
www.xicor.com
Figure 10. Byte Write Sequence
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
C
K
C
K
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
This means that the master can write 16 bytes to the
page starting at any location on that page. If the mas-
ter begins writing at location 10, and loads 12 bytes,
then the first 6 bytes are written to locations 10 through
15, and the last 6 bytes are written to locations 0
through 5. Afterwards, the address counter would point
to location 6 of the page that was just written. If the
master supplies more than 16 bytes of data, then new
data over-writes the previous data, one byte at a time.
Figure 11. Page Write Operation
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
(n)
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1
n
16)
1 0 1
0
0
address
n-1
address
10
6 Bytes
address
= 5
address pointer
ends here
Addr = 6
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.
相關(guān)PDF資料
PDF描述
X40421V14I-C Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14-A Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14-B Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14-C Dual Voltage Monitor with Intergrated CPU Supervisor
X40420S14I-A Dual Voltage Monitor with Intergrated CPU Supervisor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
X40421V14I-BT1 功能描述:IC VOLT MON DUAL SUP/SW 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40421V14I-C 功能描述:IC VOLT MON DUAL SUP/SW 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40421V14I-CT1 功能描述:IC VOLT MON DUAL SUP/SW 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40426V14I 功能描述:IC SUPERVISR CPU IIC LVS 14TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
X40426V14I-2.7 功能描述:IC SUPERVISR CPU IIC LVS 14TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件