參數(shù)資料
型號(hào): X40430S14Z-B
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: Triple Voltage Monitor with Integrated CPU Supervisor
中文描述: 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-14
文件頁數(shù): 8/26頁
文件大?。?/td> 399K
代理商: X40430S14Z-B
8
FN8251.1
May 24, 2006
Figure 2. Two Uses of Multiple Voltage Monitoring
Figure 3. V
TRIPX
Set/Reset Conditions
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A
standard read or write sequence to any slave address
byte restarts the watchdog timer and prevents the
WDO signal going active. A minimum sequence to
reset the watchdog timer requires four microprocessor
instructions namely, a Start, Clock Low, Clock High
and Stop. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer
period. The microprocessor can change these watch-
dog bits by writing to the X40430, X40431, X40434,
X40435 control register (also refer to page 20).
Figure 4. Watchdog Restart
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE (OPTIONAL)
The X40430 is shipped with standard V1, V2 and V3
threshold (V
TRIP1,
V
TRIP2,
V
TRIP3
) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40430,
X40431, X40434, X40435 trip points may be adjusted.
The procedure is described in the following situation,
and uses the application of a high voltage control sig-
nal.
6-10V
V
CC
5V
V3MON
(1.7V)
X40431-A
Unreg.
Supply
V
CC
X40431-B
RESET
V2FAIL
System
Reset
V
CC
V2FAIL
V3FAIL
System
Reset
Notice:
No external components required to monitor three voltages.
1M
V3MON
V3FAIL
V2MON
5V
Reg
3.0V
Reg
1.8V
Reg
3.3V
390K
V2MON
RESET
Power
Fail
Interrupt
V
CC
V
CC
/V2MON/V3MON
V
TRIPX
V
P
t
WC
A0h
0
7
7
0
7
0
SCL
WDO
SDA
(X = 1, 2, 3)
00h
SCL
SDA
.6μs
1.3μs
WDT Reset
Start
Stop
X40430, X40431, X40434, X40435
相關(guān)PDF資料
PDF描述
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