參數(shù)資料
型號: X40434
廠商: Intersil Corporation
英文描述: Triple Voltage Monitor with Integrated CPU Supervisor
中文描述: 三電壓監(jiān)視器集成CPU監(jiān)控
文件頁數(shù): 6/26頁
文件大?。?/td> 399K
代理商: X40434
6
FN8251.1
May 24, 2006
PIN CONFIGURATION
V3MON
WP
V
SS
V
CC
WDO
SDA
SCL
3
4
5
2
1
12
11
10
13
14
LOWLINE
NC
MR
RESET
7
6
8
9
V2MON
3
4
5
2
1
12
11
10
13
14
7
6
8
9
V3FAIL
V2FAIL
V3MON
WP
V
CC
WDO
SDA
SCL
V3FAIL
V
SS
LOWLINE
NC
MR
RESET
V2MON
V2FAIL
X40430, X40434
14 Ld SOIC, TSSOP
X40431, X40435
14 Ld SOIC, TSSOP
PIN DESCRIPTION
Pin
1
Name
V2FAIL
Function
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and goes
HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on this pin.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
second power supply with no external components. Connect V2MON to V
SS
or
V
CC
when not used. The
V2MON comparator is supplied by V2MON (X40430, X40431) or by the V
CC
input (X40434, X40435).
LOWLINE
Early Low V
CC
Detect.
This CMOS output signal goes LOW when
V
CC
< V
TRIP1
and goes high when
V
CC
> V
TRIP1
.
NC
No connect.
MR
Manual Reset Input.
Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will re-
main HIGH/LOW until the pin is released and for the t
PURST
thereafter.
RESET/
RESET
ever V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and for
t
PURST
thereafter.
RESET Output.
(X40430, X40434) This pin is an active HIGH CMOS output which goes HIGH when-
ever V
CC
falls below V
TRIP1
voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (t
PURST
) on power-up. It will also stay active until manual reset is released and for
t
PURST
thereafter.
V
SS
Ground
SDA
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a
pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW and
followed by a stop condition) restarts the Watchdog timer. The absence of this transition within the
watchdog time out period results in WDO going active.
SCL
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
WP
Write Protect.
WP HIGH prevents writes to any location in the device (including all the registers). It has
an internal pull down resistor (>10M
typical).
V3MON
V3 Voltage Monitor Input.
When the V3MON input is less than the V
TRIP3
voltage, V3FAIL goes LOW.
This input can monitor an unregulated power supply with an external resistor divider or can monitor a
third power supply with no external components. Connect V3MON to V
SS
or
V
CC
when not used. The
V3MON comparator is supplied by the V3MON input.
V3FAIL
V3 Voltage Fail Output.
This open drain output goes LOW when V3MON is less than V
TRIP3
and goes
HIGH when V3MON exceeds V
TRIP3
. There is no power-up reset delay circuitry on this pin.
WDO
WDO Output.
WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
V
CC
Supply Voltage
2
V2MON
3
4
5
6
RESET Output.
(X40431, X40435) This open drain pin is an active LOW output which goes LOW when-
7
8
9
10
11
12
13
14
X40430, X40431, X40434, X40435
相關PDF資料
PDF描述
X40434S14IZ-A Triple Voltage Monitor with Integrated CPU Supervisor
X40434S14IZ-B Triple Voltage Monitor with Integrated CPU Supervisor
X40434S14Z-A Triple Voltage Monitor with Integrated CPU Supervisor
X40434S14Z-B Triple Voltage Monitor with Integrated CPU Supervisor
X4323 RTC Module With CPU Supervisor
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