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參數(shù)資料
| 型號： | X40434S14IZ-A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Triple Voltage Monitor with Integrated CPU Supervisor |
| 中文描述： | 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-14 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 399K |
| 代理商： | X40434S14IZ-A |
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12
FN8251.1
May 24, 2006
Figure 7. Valid Data Changes on the SDA Bus
At power-up, the FDR is defaulted to all “0”. The sys-
tem needs to initialize this register to all “1” before the
actual monitoring can take place. In the event that any
one of the monitored sources fail, the corresponding
bit in the register will change from a “1” to a “0” to indi-
cate the failure. At this moment, the system should
perform a read to the register and note the cause of
the reset. After reading the register the system should
reset the register back to all “1” again. The state of the
FDR can be read at any time by performing a random
read at address 0FFh, using the special preamble.
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one
byte of data is read by the register read operation.
MRF, Manual Reset Fail Bit (Volatile)
The MRF bit will be set to “0” when Manual Reset
input goes active.
WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will be set to “0” when the WDO goes
active.
LV1F, Low V
CC
Reset Fail Bit (Volatile)
The LV1F bit will be set to “0” when V
CC
(V1MON)
falls below V
TRIP1
.
LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls
below V
TRIP2
.
LV3F, Low V3MON Reset Fail Bit (Volatile)
The LV3F bit will be set to “0” when the V3MON falls
below V
TRIP3
.
SERIAL INTERFACE
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 8.
Serial Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
Figure 8. Valid Start and Stop Conditions
SCL
SDA
Data Stable
Data Change
Data Stable
SCL
SDA
Start
Stop
X40430, X40431, X40434, X40435
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X40434S14IZ-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X40434S14Z-A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X40434S14Z-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X40434V141Z-B | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| X40434V14-A | 功能描述:IC VOLT MON TRPL EEPROM 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
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