參數(shù)資料
型號(hào): X40435S14IZ-B
廠商: INTERSIL CORP
元件分類(lèi): 電源管理
英文描述: Triple Voltage Monitor with Integrated CPU Supervisor
中文描述: 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-14
文件頁(yè)數(shù): 16/26頁(yè)
文件大?。?/td> 399K
代理商: X40435S14IZ-B
16
FN8251.1
May 24, 2006
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
hex
General Purpose Memory Organization, A8:A0
Address: 000h to 1FFh
General Purpose Memory Array Configuration
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x = 0 is for Array, x = 1 is for Control Register or
Fault Detection Register.
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 14. X40430, X40431, X40434, X40435
Addressing
– last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power-up condition.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for
t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
Figure 15. Current Address Read Sequence
.
Memory Address
A8:A0
000h
0FFh
100h
1FFh
Lower 256 bytes
Upper 256 bytes
Block Protect Option
General Purpose Memory
Control Register
Fault Detection Register
1
1
1
0
0
0
1
1
1
0
1
1
A8 R/W
1
0
Word Address
Slave Byte
0
0
0
0
0
0
R/W
R/W
General Purpose Memory
Control Register
Fault Detection Register
A7
1
1
A6
1
1
A5
1
1
A4
1
1
A1
1
1
A0
1
1
A3
1
1
A2
1
1
S
t
a
r
t
S
t
o
p
Slave
Address
Data
SDA Bus
Signals from
the Slave
Signals from
the Master
1
A
C
K
1 0 1 0
0
0
X40430, X40431, X40434, X40435
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X40435S14Z-A 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor
X40435S14Z-B 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor
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X40435V14-AT1 功能描述:IC VOLT MON TRPL EEPROM 14-TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類(lèi)型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
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