參數(shù)資料
型號: X40626S14-2.7A
元件分類: CPU監(jiān)測
英文描述: RTC Module With CPU Supervisor
中文描述: 時鐘模塊CPU監(jiān)控
文件頁數(shù): 2/23頁
文件大?。?/td> 516K
代理商: X40626S14-2.7A
X40626
REV 1.1.15 2/11/04
Characteristics subject to change without notice.
2 of 23
www.xicor.com
operating level and stabilizes. Four industry standard Vtrip
thresholds are available. However, Xicor’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software protocol
allowing operation on an I
C bus.
Protection. The
2
The device utilizes Xicor’s proprietary Direct Write
providing a minimum endurance of 100,000 page write
cycles and a minimum data retention of 100 years.
cell,
PIN CONFIGURATION
S
1
NC
V
SS
V
CC
NC
V2MON
V2FAIL
WP
3
4
5
2
1
12
11
10
13
14
14 Pin SOIC/TSSOP
S
0
RESET
6
7
9
8
NC
SDA
SCL
NC
PIN FUNCTION
Pin
Name
NC
S
S
RESET
Function
1, 4, 6, 13
2
3
5
No Internal Connections
Device Select Input
Device Select Input
Reset Output
falls below the minimum V
imum V
CC
sense level for typically 200ms. RESET goes active if the Watchdog Timer is
enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time-
out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET
goes active on power up and remains active for typically 200ms after the power supply
stabilizes.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It has
an open drain output and may be wire ORed with other open drain or open collector outputs.
This pin requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the
Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time-out
period results in RESET going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than
V
TRIP2
and goes HIGH when V2MON exceeds V
circuitry on this pin. This circuit works independently from the Low V
switch circuits. Connect V2FAIL to VSS when not used.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
goes LOW. This input can monitor an unregulated power supply with an external resistor
divider or can monitor a second power supply with no external components. Connect
V2MON to V
SS
or V
CC
when not used. There is no hysteresis in the V2MON comparator
circuits.
Write Protect.
WP HIGH used in conjunction with WPEN bit prevents writes to the control
register.
Supply Voltage
0
1
.
RESET is an active LOW, open drain output which goes active whenever V
CC
sense level. It will remain active until V
CC
rises above the min-
7
8
V
SDA
SS
9
10
SCL
V2FAIL
TRIP2
. There is no power up reset delay
CC
reset and battery
11
V2MON
TRIP2
voltage, V2FAIL
12
WP
14
V
CC
相關PDF資料
PDF描述
X40626S14I RTC Module With CPU Supervisor
X40626S14I-2.7 RTC Module With CPU Supervisor
X40626S14I-2.7A RTC Module With CPU Supervisor
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X40626V14-2.7 RTC Module With CPU Supervisor
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