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參數(shù)資料
| 型號(hào)： | X4283AL |
| 元件分類： | EEPROM |
| 英文描述： | CPU Supervisor with 128K EEPROM |
| 中文描述： | CPU監(jiān)控與128K的EEPROM的 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 412K |
| 代理商： | X4283AL |
X4283/85 – Preliminary Information
Characteristics subject to change without notice.
2 of 22
REV 1.17 11/27/00
www.xicor.com
standard Vtrip thresholds are available, however, Xicor’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock protection. The
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software proto-
col allowing operation on an 2-wire bus.
PIN CONFIGURATION
S
1
V
SS
V
CC
WP
SDA
SCL
3
4
2
1
6
5
7
8
S
0
RST/RST
V
CC
S
0
S
1
SCL
SDA
RST/RST
V
SS
3
4
2
1
6
5
7
8
WP
8-Pin JEDEC SOIC
8-Pin TSSOP
PIN DESCRIPTION
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
Name
S
S
RESET/
RESET
Function
0
Device Select Input
Device Select Input
Reset Output
goes active whenever V
active until V
RESET goes active if the Watchdog Timer is enabled and SDA remains either
HIGH or LOW longer than the selectable Watchdog time out period. A falling edge
on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes
active on power up and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
Supply Voltage
1
.
RESET/RESET is an active LOW/HIGH, open drain output which
falls below the minimum V
CC
rises above the minimum V
CC
sense level for 250ms. RESET/
CC
CC
sense level. It will remain
4
5
6
7
V
SDA
SS
6
7
8
1
SCL
WP
8
2
V
CC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X4283AN | CPU Supervisor with 128K EEPROM |
| X4283AP | CPU Supervisor with 128K EEPROM |
| X4283S8-2.7 | CPU Supervisor with 128K EEPROM |
| X4283V8-2.7 | CPU Supervisor with 128K EEPROM |
| X4283V8-4.5A | CPU Supervisor with 128K EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X4283AM | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:CPU Supervisor with 128K EEPROM |
| X4283AN | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:CPU Supervisor with 128K EEPROM |
| X4283AP | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:CPU Supervisor with 128K EEPROM |
| X4283F | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:CPU Supervisor with 128K EEPROM |
| X4283G | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:CPU Supervisor with 128K EEPROM |
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