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參數(shù)資料
| 型號： | X4325V8I-4.5A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | 4.40 MM, PLASTIC, MO-153AC, TSSOP-8 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 333K |
| 代理商： | X4325V8I-4.5A |
2
FN8122.0
March 29, 2005
PIN CONFIGURATION
PIN FUNCTION
S
1
V
SS
V
CC
WP
SDA
SCL
3
4
2
1
6
5
7
8
8-Pin JEDEC SOIC
S
0
RST/RST
V
CC
S
0
S
1
SCL
SDA
RST/RST
V
SS
3
4
2
1
6
5
7
8
WP
8-Pin TSSOP
Pin
(SOIC)
1
2
3
Pin
(TSSOP)
3
4
5
Name
S
0
S
1
RESET/
RESET
Function
Device Select Input
Device Select Input
Reset Output
.
RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
falls below the minimum V
CC
sense level. It will remain ac-
tive until V
CC
rises above the minimum V
CC
sense level for 250ms. RESET/RESET
goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW
longer than the selectable Watchdog time out period. A falling edge on SDA, while
SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power-up-
power-up and remains active for 250ms after the power supply stabilizes.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the de-
vice. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. This pin requires a pull up resistor and the input buffer is al-
ways active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH used in conjunction with WPEN bit prevents writes to the
control register.
Supply Voltage
4
5
6
7
V
SS
SDA
6
7
8
1
SCL
WP
8
2
V
CC
X4323, X4325
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