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參數(shù)資料
| 型號： | X4645V8I-4.5A |
| 元件分類： | EEPROM |
| 英文描述： | CPU Supervisor with 64K EEPROM |
| 中文描述： | CPU監(jiān)控與64K的EEPROM的 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 408K |
| 代理商： | X4645V8I-4.5A |
X4643/5 – Preliminary Information
Characteristics subject to change without notice.
5 of 22
REV 1.26 4/30/02
www.xicor.com
Figure 4. V
TRIP
Programming Sequence
V
TRIP
Programming
Apply 5V to V
CC
Decrement V
CC
(V
CC
= V
CC
- 50mV)
RESET pin
goes active
Measured V
TRIP
-
Desired V
TRIP
DONE
Execute
Reset V
TRIP
Sequence
Set V
CC
= V
CC
Applied =
Desired V
TRIP
Execute
Set V
Sequence
New V
CC
Applied =
Old V
CC
Applied + Error
Execute
Reset V
Sequence
New V
CC
Applied =
Old V
CC
Applied - Error
Error
≤
–Emax
–Emax < Error < Emax
YES
NO
Error
≥
Emax
Emax = Maximum Allowed V
TRIP
Error
Control Register
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
The user must issue a stop after sending this byte to the
register to initiate the nonvolatile cycle that stores WD1,
and WD0. The X4643/5 will not acknowledge any data
bytes written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
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