參數(shù)資料
型號: X4C105
廠商: Intersil Corporation
元件分類: CPU監(jiān)測
英文描述: RTC Module With CPU Supervisor
中文描述: 時鐘模塊CPU監(jiān)控
文件頁數(shù): 3/19頁
文件大?。?/td> 296K
代理商: X4C105
3
FN8124.0
March 18, 2005
Capacitor Backup Circuit
The diagram in Figure 1 shows a representation of the capacitor backup circuit.
Figure 1.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 2.
Figure 2. Valid Data Changes on the SDA Bus
Start
NOVRAM
AUTOSTORE
To Internal
Voltage Supply
HIGH when
V
CC
> V
TRIP
LOW when
V
CC
<V
TRIP
-0.2V
V
TRIP
V
CC
CAP
SCL
SDA
Data Stable
Data Change
Data Stable
X4C105
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