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參數(shù)資料
| 型號： | X4C105V20I |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 296K |
| 代理商： | X4C105V20I |
12
FN8124.0
March 18, 2005
SERIAL AC SPECIFICATIONS
T
A
= -40
°
C to +85
°
C, V
CC
= +3.0V to +3.6V, unless otherwise specified.
Notes: (7) This parameter is periodically sampled and not 100% tested.
(8) Cb = total capacitance of one bus line in pF.
SERIAL TIMING DIAGRAMS
Bus Timing
Symbol
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
t
SU: S1, S2,WP
t
HD: S1, S2,WP
Cb
Parameter
400kHz Option
Min.
0
0
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb
(8)
20 +.1Cb
(8)
0.4
0.4
Unit
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
ms
ms
pF
Max.
400
50
0.9
SCL clock frequency
Pulse width of spikes to be suppressed by the input filter
SCL LOW to SDA data out valid
Time the bus must be free before a new transmission can start
Clock LOW time
Clock HIGH time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
Data output hold time
SDA and SCL rise time
SDA and SCL fall time
S1, S2, and WP setup time
S1, S2, and WP hold time
Capacitive load for each bus line
300
300
400
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
X4C105
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