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參數(shù)資料
| 型號： | X5083S8I-4.5A |
| 元件分類： | CPU監(jiān)測 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時鐘模塊CPU監(jiān)控 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 115K |
| 代理商： | X5083S8I-4.5A |
X5083
Characteristics subject to change without notice.
6 of 21
REV 1.1.6 6/25/02
www.xicor.com
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 7). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows.
Status Register/Block Lock/WDT Byte
Block Lock Memory
Xicor’s block lock memory provides a flexible mecha-
nism to store and lock system ID and parametric infor-
mation. There are seven distinct block lock memory
areas within the array which vary in size from one page
to as much as half of the entire array. These areas and
associated address ranges are block locked by writing
the appropriate two byte block lock instruction to the
device as described in Table 1 and Figure 9. Once a
block lock instruction has been completed, that block
lock setup is held in the nonvolatile status register until
the next block lock instruction is issued. The sections
of the memory array that are block locked can be read
but not written until block lock is removed or changed.
7
0
6
0
5
0
4
3
2
1
0
WD1
WD0
BL2
BL1
BL0
Table 1. Instruction Set and Block Lock Protection Byte Definition
Instruction Format
0000 0110
0000 0100
0000 0001
Instruction Name and Operation
WREN: set the write enable latch (write enable operation)
WRDI: reset the write enable latch (write disable operation)
Write status instruction—followed by:
Block lock/WDT byte: (See Figure 1)
000WD
1
WD
2
000 --->no block lock: 00h-00h
000WD
1
WD
2
001 --->block lock Q1: 0000h-00FFh --->lower quadrant (Q1)
000WD
1
WD
2
010 --->block lock Q2: 0100h-01FFh --->Q2
000WD
1
WD
2
011 --->block lock Q3: 0200h-02FFh --->Q3
000WD
1
WD
2
100 --->block lock Q4: 0300h-03FFh --->upper quadrant (Q4)
000WD
1
WD
2
101 --->block lock H1: 0000h-01FFh
000WD
1
WD
2
110 --->block lock P0: 0000h-000Fh
000WD
1
WD
2
111 --->block lock Pn: 03F0h-03FFh
READ STATUS: reads status register & provides write in progress status on SO pin
WRITE: write operation followed by address and data
READ: read operation followed by address
--->none of the array
--->lower half of the array (H1)
--->lower page (P0)
--->upper page (PN)
0000 0101
0000 0010
0000 0011
Watchdog Timer
The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction. A change to
the Watchdog Timer, either setting a new time out
period or turning it off or on, takes effect, following
either the next command (read or write) or cycling the
power to the device.
The recommended procedure for changing the Watch-
dog Timer settings is to do a WREN, followed by a
write status register command. Then execute a soft-
ware loop to read the status register until the MSB of
the status byte is zero. A valid alternative is to do a
WREN, followed by a write status register command.
Then wait 10ms and do a read status command.
Table 2. Watchdog Timer Definition
Status Register Bits
WD1
0
0
1
1
Watchdog Time Out
(Typical)
1.4 seconds
600 milliseconds
200 milliseconds
disabled (factory default)
WD0
0
1
0
1
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| X5083S8IT1 | 功能描述:IC SUPERVISOR CPU 8K EE 8-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復(fù)位:低有效 復(fù)位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
| X5083S8IT2 | 功能描述:IC SUPERVISOR CPU 8K EE 8-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復(fù)位:低有效 復(fù)位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
| X5083S8IZ | 功能描述:IC SUPERVISOR CPU 8K EE 8-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:低有效 復(fù)位超時:最小為 600 ms 電壓 - 閥值:3.8V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:帶卷 (TR) |
| X5083S8IZ-2.7 | 功能描述:IC SUPERVISOR CPU 8K EE 8-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:低有效 復(fù)位超時:最小為 600 ms 電壓 - 閥值:3.8V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:帶卷 (TR) |
| X5083S8IZ-2.7A | 功能描述:IC CPU SUPERV 8K EEPROM 8-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:低有效 復(fù)位超時:最小為 600 ms 電壓 - 閥值:3.8V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:帶卷 (TR) |
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