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參數資料
| 型號： | X5083V8-2.7 |
| 元件分類： | CPU監(jiān)測 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時鐘模塊CPU監(jiān)控 |
| 文件頁數： | 5/21頁 |
| 文件大?。?/td> | 115K |
| 代理商： | X5083V8-2.7 |
X5083
Characteristics subject to change without notice.
5 of 21
REV 1.1.6 6/25/02
www.xicor.com
Figure 4. V
TRIP
Programming Sequence
V
TRIP
Programming
Apply 5V to V
CC
Decrement V
CC
(V
CC
= V
CC
- 50mV)
RESET pin
goes active
Measured V
TRIP
-
Desired V
TRIP
DONE
Execute
Reset V
TRIP
Sequence
Set V
CC
= V
CC
Applied =
Desired V
TRIP
Execute
Set V
Sequence
New V
CC
Applied =
Old V
CC
Applied + Error
Execute
Reset V
Sequence
New V
CC
Applied =
Old V
CC
Applied - Error
Error
≤
–Emax
–Emax < Error < Emax
YES
NO
Error
≥
Emax
Emax = Maximum Desired Error
SPI Serial Memory
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device monitors the bus and asserts RESET out-
put if the watchdog timer is enabled and there is no bus
activity within the user selectable time out period or the
supply voltage falls below a preset minimum V
TRIP
.
The device contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising edge of SCK. CS must be LOW during the
entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
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| X5083V8-4.5A | 功能描述:IC SUPERVISOR CPU 8K EE 8-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數目:1 輸出:推挽式，圖騰柱 復位:低有效 復位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應商設備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
| X5083V8I | 功能描述:IC SUPERVISOR CPU 8K EE 8-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數目:1 輸出:推挽式，圖騰柱 復位:低有效 復位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應商設備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
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| X5083V8I-2.7A | 功能描述:IC SUPERVISOR CPU 8K EE 8-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數目:1 輸出:推挽式，圖騰柱 復位:低有效 復位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應商設備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
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