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參數(shù)資料
| 型號(hào)： | X5165S8I-2.7T1 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | THYRISTOR MODULE, 95A, 0800V; Thyristor/Triac type:Thyristor; Voltage, Vdrm:800V; Current, It rms:150A; Current, Itsm:2000A; Current, Igt:150mA; Voltage, Vgt:3.0V; Case style:SEMIPACK 1; Centres, fixing:80mm; Current, It av:95A; RoHS Compliant: Yes |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 117K |
| 代理商： | X5165S8I-2.7T1 |
X5163/X5165 – Preliminary Information
Characteristics subject to change without notice.
5 of 21
REV 1.1 3/5/01
www.xicor.com
Figure 4. Sample V
TRIP
Reset Circuit
1
2
3
4
8
7
6
5
X5163/65
V
TRIP
Adj.
Program
NC
NC
V
P
Reset V
TRIP
Test
V
TRIP
Set V
TRIP
NC
RESET
4.7K
4.7K
10K
10K
+
SPI SERIAL MEMORY
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is for-
matted as follows:
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
7
6
5
4
3
2
1
0
WPEN
FLB
WD1
WD0
BL1
BL0
WEL
WIP
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