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參數(shù)資料
| 型號： | X5165V14-2.7A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | PLASTIC, MO-153AC, TSSOP-14 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大小： | 117K |
| 代理商： | X5165V14-2.7A |
X5163/X5165 – Preliminary Information
Characteristics subject to change without notice.
6 of 21
REV 1.1 3/5/01
www.xicor.com
Table 1. Instruction Set
Note:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
Instruction Name
WREN
SFLB
WRDI/RFLB
RSDR
WRSR
READ
WRITE
Instruction Format*
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
WREN CMD Status Register
Device Pin
Block
Block
Status Register
WPEN, BL0, BL1,
WD0, WD1
Protected
Protected
Writable
Writable
WEL
0
1
1
1
WPEN
X
1
0
X
WP#
X
0
X
1
Protected Block
Protected
Protected
Protected
Protected
Unprotected Block
Protected
Writable
Writable
Writable
The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to pro-
tect one quarter, one half, all or none of the EEPROM
array. Any portion of the array that is block lock pro-
tected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable block lock
protection of that portion of memory.
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time Out Period. These nonvolatile bits are
programmed with the WRSR instruction.
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The Flag bit is automatically
reset upon power up. This flag can be used by the sys-
tem to determine whether a reset occurs as a result of
a watchdog time out or power failure.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
ROM function (Table 2). WP is LOW and WPEN bit pro-
grammed HIGH disables all Status Register Write
Operations.
Status
Register Bits
BL1
0
0
1
1
Array Addresses Protected
X516x
None
$0600–$07FF
$0400–$07FF
$0000–$07FF
BL0
0
1
0
1
Status Register Bits
WD1
0
0
1
1
Watchdog Time Out
(Typical)
1.4 seconds
600 milliseconds
200 milliseconds
disabled
WD0
0
1
0
1
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