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參數(shù)資料
| 型號： | X5323P-2.7A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | MODULE ZIGBEE 2.4GHZ 1MW |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 360K |
| 代理商： | X5323P-2.7A |
4
FN8131.1
October 27, 2005
PIN CONFIGURATION
PIN DESCRIPTION
Pin
(SOIC/PDIP)
1
Pin
TSSOP
1
Name
CS/WDI
Function
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at a
high impedance state. Unless a nonvolatile write cycle is underway, the
device will be in the standby power mode. CS LOW enables the device, placing
it in the active power mode. Prior to the start of any operation after power-up, a
HIGH to LOW transition on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock.
The serial clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits present
on the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to
“l(fā)ock” the setting of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output
.
RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever V
CC
falls below the minimum V
CC
sense level. It will re-
main active until V
CC
rises above the minimum V
CC
sense level for 200ms. RE-
SET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes
active on power-up at about 1V and remains active for 200ms after the power
supply stabilizes.
No internal connections
2
2
SO
5
8
SI
6
9
SCK
3
6
WP
4
8
7
7
V
SS
V
CC
RESET/
RESET
14
13
3-5,10-12
NC
X5323/25
X5323/25
8 Ld SOIC/PDIP
CS/WDT
WP
SO
1
2
3
4
RESET/RESET
8
7
6
5
V
CC
14 Ld TSSOP
SO
NC
WP
V
SS
1
2
3
4
5
6
7
SCK
SI
14
13
12
11
10
9
8
V
CC
RESET/RESET
NC
V
SS
SCK
SI
CS
/WDT
NC
NC
NC
NC
X5323, X5325
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