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參數(shù)資料
| 型號： | X5323V14Z-2.7-T1 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 341K |
| 代理商： | X5323V14Z-2.7-T1 |
4
FN8131.2
June 30, 2008
Pin Descriptions
PIN NUMBER
(SOIC/PDIP)
PIN NUMBER
TSSOP
PIN NAME
PIN FUNCTION
11
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the stand-by power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation
after power-up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.
22
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
58
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
69
SCK
Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
36
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “l(fā)ock” the setting
of the watchdog timer control and the memory write protect bits.
47
VSS
Ground
814
VCC
Supply Voltage
7
13
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
3 to 5,10 to 12
NC
No internal connections
X5323, X5325
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相關代理商/技術參數(shù) |
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| X5323V14Z-4.5A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 32Kb SPI EEPROM |
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| X5325P | 功能描述:IC CPU SUPRV 32K EE RST HI 8DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復位:低有效 復位超時:標準傳輸延遲為 60 µs 電壓 - 閥值:3V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應商設備封裝:SOT-23-5 包裝:Digi-Reel® 其它名稱:LM8364BALMF30DKR |
| X5325P-2.7 | 功能描述:IC SUPERVISOR CPU 32K EE 8-DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復位:低有效 復位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應商設備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
| X5325P-2.7A | 功能描述:IC SUPERVISOR CPU 32K EE 8-DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復位:低有效 復位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應商設備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
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