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參數(shù)資料
| 型號： | X5325S8I-2.7A |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 200K |
| 代理商： | X5325S8I-2.7A |
X5323/X5325
Characteristics subject to change without notice.
2 of 21
REV 1.1.2 11/13/01
www.xicor.com
PIN CONFIGURATION
PIN DESCRIPTION
Pin
(SOIC/PDIP)
Pin
TSSOP
Name
Function
11
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the
device will be in the standby power mode. CS LOW enables the device, placing
it in the active power mode. Prior to the start of any operation after power up, a
HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
22
SO
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
58
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin.The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB rst.
6
9
SCK
Serial Clock. The serial clock controls the serial bus timing for data input and
output.The rising edge of SCK latches in the opcode, address, or data bits present
on the SI pin. The falling edge of SCK changes the data output on the SO pin.
36
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“l(fā)ock” the setting of the watchdog timer control and the memory write protect bits.
47
VSS
Ground
814
VCC
Supply Voltage
7
13
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever VCC falls below the minimum VCC sense level. It
will remain active until VCC rises above the minimum VCC sense level for
200ms. RESET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes
active on power up at about 1V and remains active for 200ms after the power
supply stabilizes.
3-5,10-12
NC
No internal connections
X5323/25
8-Lead SOIC/PDIP
CS/WDT
WP
SO
1
2
3
4
RESET/RESET
8
7
6
5
VCC
14-Lead TSSOP
SO
WP
VSS
1
2
3
4
5
6
7
SCK
SI
14
13
12
11
10
9
8
NC
VCC
NC
VSS
SCK
SI
CS/WDT
NC
RESET/RESET
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