參數(shù)資料
型號： X5643S8-2.7A
元件分類： EEPROM
英文描述： SPI Serial EEPROM with Supervisory Features
中文描述： SPI串行EEPROM，帶有監(jiān)控功能
文件頁數(shù)： 7/22頁
文件大?。?/td> 106K
代理商： X5643S8-2.7A
X5643/X5645
Characteristics subject to change without notice.
7 of 22
Figure 5. Read EEPROM Array Sequence
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
16 Bit Address
15 14 13
3
2
1
0
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the status register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the status register.
When WP is HIGH, all functions, including nonvolatile
writes to the status register operate normally. Setting
the WPEN bit in the status register to “0” blocks the WP
pin function, allowing writes to the status register when
WP is HIGH or LOW. Setting the WPEN bit to “1” while
the WP pin is LOW activates the programmable ROM
mode, thus requiring a change in the WP pin prior to
subsequent status register changes. This allows manu-
facturing to install the device in a system with WP pin
grounded and still be able to program the status regis-
ter. Manufacturing can then load configuration data,
manufacturing time and other parameters into the
EEPROM, then set the portion of memory to be pro-
tected by setting the block lock bits, and finally set the
“OTP mode” by setting the WPEN bit. Data changes
now require a hardware change.
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction
is transmitted to the device, followed by the 16-bit address.
After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out
on the SO line. The data stored in memory at the next
address can be read sequentially by continuing to provide
clock pulses. The address is automatically incremented to
the next higher address after each byte of data is shifted
out. When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the read EEPROM
array sequence (Figure 1).
To read the status register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
status register are shifted out on the SO line. Refer to
the read status register sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.
相關PDF資料
PDF描述
X5643S8I-4.5A SPI Serial EEPROM with Supervisory Features
X5645S14-1.8 SPI Serial EEPROM with Supervisory Features
X5643S8-1.8 SPI Serial EEPROM with Supervisory Features
X5645S8-1.8 SPI Serial EEPROM with Supervisory Features
X5645S8-2.7 SPI Serial EEPROM with Supervisory Features
相關代理商/技術參數(shù)
參數(shù)描述
X5643S8I-4.5A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features
X5645 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:CPU Supervisor with 64Kbit SPI EEPROM
X5645P 功能描述:IC CPU SUPRV 64K EE RST HI 8DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復位:低有效 復位超時:標準傳輸延遲為 60 µs 電壓 - 閥值:3V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應商設備封裝:SOT-23-5 包裝:Digi-Reel® 其它名稱:LM8364BALMF30DKR
X5645P-4.5A 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:CPU Supervisor with 64Kbit SPI EEPROM
X5645S14 功能描述:IC CPU SUPRV 64K EE RST HI SO14 RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:1 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復位:低有效 復位超時:標準傳輸延遲為 60 µs 電壓 - 閥值:3V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應商設備封裝:SOT-23-5 包裝:Digi-Reel® 其它名稱:LM8364BALMF30DKR
發(fā)布緊急采購，3分鐘左右您將得到回復。