- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371268 > X5645S14-4.5A RTC Module With CPU Supervisor PDF資料下載
參數(shù)資料
| 型號： | X5645S14-4.5A |
| 元件分類： | CPU監(jiān)測 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時鐘模塊CPU監(jiān)控 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 117K |
| 代理商： | X5645S14-4.5A |
X5643/X5645
Characteristics subject to change without notice.
2 of 19
REV 1.1.1 3/5/01
www.xicor.com
PIN CONFIGURATION
Pin
PDIP
1
Pin
SOIC
2 & 3
Pin
TSSOP
2
Name
CS/WDI
Function
Chip Select Input.
at a high impedance state. Unless a nonvolatile write cycle is underway, the
device will be in the standby power mode. CS LOW enables the device, plac-
ing it in the active power mode. Prior to the start of any operation after power
up, a HIGH to LOW transition on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the in-
put data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock.
The serial clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to
“l(fā)ock” the setting of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output
.
RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V
CC
falls below the minimum V
It will remain active until V
CC
rises above the minimum V
200ms. RESET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET
goes active on power up at about 1V and remains active for 200ms after the
power supply stabilizes.
No internal connections
CS HIGH, deselects the device and the SO output pin is
2
4
3
SO
5
9
13
SI
6
10
14
SCK
3
5
7
WP
4
8
7
6
8
19
18
V
V
SS
12 & 13
11
CC
RESET/
RESET
CC
sense level for
sense level.
CC
1, 7, 8,
14
1, 4–6,
9–12,
15–17, 20
NC
8-Lead PDIP
CS/WDI
WP
SO
1
2
3
4
RESET/RESET
8
7
6
5
14-Lead SOIC
SO
WP
V
SS
1
2
3
4
5
6
7
RESET/RESET
SCK
SI
14
13
12
11
10
9
8
NC
V
CC
V
CC
NC
X5643/45
SCK
SI
CS/WDI
NC
X5643/45
NC
CS/WDI
V
CC
V
SS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X5645S14I | RTC Module With CPU Supervisor |
| X5645S14I-4.5A | RTC Module With CPU Supervisor |
| X5645X14I-4.5A | Analog IC |
| X5645P | RTC Module With CPU Supervisor |
| X5645S14 | RTC Module With CPU Supervisor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X5645S14I | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:CPU Supervisor with 64Kbit SPI EEPROM |
| X5645S14I-2.7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| X5645S14I-4.5A | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:CPU Supervisor with 64Kbit SPI EEPROM |
| X5645S8-1.8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X5645S8-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。