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參數(shù)資料
| 型號： | X5645S14I-4.5A |
| 元件分類： | CPU監(jiān)測 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時鐘模塊CPU監(jiān)控 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 117K |
| 代理商： | X5645S14I-4.5A |
X5643/X5645
Characteristics subject to change without notice.
8 of 19
REV 1.1.1 3/5/01
www.xicor.com
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 4).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be “0”.
While the write is in progress following a status register or
EEPROM sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be high.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The write enable latch is reset.
– The flag bit is reset.
– Reset signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the write
enable latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
Figure 6. Read Status Register Sequence
Figure 7. Write Enable Latch Sequence
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
0
1
2
3
4
5
6
7
CS
SI
SCK
High Impedance
SO
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| X5645X14I-4.5A | Analog IC |
| X5645P | RTC Module With CPU Supervisor |
| X5645S14 | RTC Module With CPU Supervisor |
| X5645S14-2.7 | RTC Module With CPU Supervisor |
| X5645S14-2.7A | RTC Module With CPU Supervisor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
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| X5645S8-1.8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X5645S8-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X5645X14I-4.5A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| X5648 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 64Kbit SPI EEPROM |
| X5648P | 功能描述:IC SUPERVISOR CPU 64K EE 8-DIP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復位:低有效 復位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應商設備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
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