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參數(shù)資料
| 型號(hào)： | X5649 |
| 元件分類： | CPU監(jiān)測 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時(shí)鐘模塊CPU監(jiān)控 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大小： | 120K |
| 代理商： | X5649 |
X5648/X5649
5
SPI SERIAL MEMORY
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s Block Lock
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
TM
Protection. The
The device utilizes Xicor’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
TM
cell,
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must
be LOW during the entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is latched
on the first rising edge of SCK after CS goes LOW. Data
is output on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
Write Enable Latch
The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is
formatted as follows:
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
7
6
5
0
4
0
3
2
1
0
WPEN
FLB
BL1
BL0
WEL
WIP
Table 1. Instruction Set
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
Instruction Name
WREN
Instruction Format*
0000 0110
Operation
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
SFLB
0000 0000
WRDI/RFLB
0000 0100
RSDR
0000 0101
WRSR
0000 0001
READ
0000 0011
WRITE
0000 0010
WREN CMD
STATUS
REGISTER
DEVICE
PIN
BLOCK
BLOCK
STATUS
REGISTER
WPEN, BL0, BL1
WD0, WD1
Protected
Protected
Writable
Writable
WEL
0
1
1
1
WPEN
X
1
0
X
WP#
X
0
X
1
PROTECTED
BLOCK
Protected
Protected
Protected
Protected
UNPROTECTED
BLOCK
Protected
Writable
Writable
Writable
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