X68257
2
PIN DESCRIPTIONS
Address/Data (A/D
0
–A/D
7
)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while AS is HIGH. After AS
transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on R/
W
,
SEL
, and
CE.
Addresses (A
8
–A
14
)
High order addresses flow into the device when AS = V
IH
and are latched when AS goes LOW.
Chip Enable (
CE
)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, AS is LOW, and CE
is LOW, the X68257 is placed in the low power standby
mode.
Chip Enable (CE)
Chip Enable is active HIGH. When CE is used to select
the device, the CE must be tied HIGH.
Program Store Enable (
SEL
)
When the X68257 is to be used in a 68XX-based
system,
SEL
is tied to V
SS
.
Read/Write (R/
W
)
When the X68257 is to be used in a 68XX-based
system, R/
W
is tied directly to the microcontroller’s R/
W
output.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is HIGH and are latched when AS transitions
from a HIGH to LOW.
PIN CONFIGURATION
PIN NAMES
Symbol
Description
AS
A/D
0
–A/D
7
A
8
–A
14
E
R/
W
CE,
CE
SEL
V
SS
V
CC
NC
Address Strobe
Address Inputs/Data I/O
Address Inputs
Enable Input
Read/Write Input
Chip Enable
Device Select—Connect to V
SS
Ground
Supply Voltage
No Connect
6539 PGM T01.2
6539 FHD F01.3
A14
A12
AS
SEL
CE
NC
NC
NC
NC
NC
A/D0
A/D1
A/D2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
R/W
A13
A8
A9
A11
E
A10
CE
A/D7
A/D6
A/D5
A/D4
A/D3
PDIP
SOIC
X68257
6539 FHD F01A.5
A
SEL
CE
NC
NC
NC
NC
NC
NC
A/D0
A8
A9
A11
NC
E
A10
CE
A/D7
A/D6
A1
A1
VC
R
A1
A1
A2
VS
N
A3
A4
A5
3
2
1 32 31
15 16 17 18 19
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
X68257
PLCC
14
20
4
30
29
N