X68257
3
PRINCIPLES OF OPERATION
The X68257 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The X68257
provides 32K-bytes of 5V E
2
PROM which can be used
either for program storage, data storage, or a combina-
tion of both, in systems based upon Von Neumann
(68XX) architectures. The X68257 incorporates the
interface circuitry normally needed to decode the control
signals and demultiplex the address/data bus to provide
a “seamless” interface.
The interface inputs on the X68257 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip micro-
controller.
The X68257 features the industry standard 5V E
2
PROM
characteristics such as byte or page mode write and
Toggle Bit Polling.
DEVICE OPERATION
Motorola 68XX operation requires the microcontroller
AS, E, and R/
W
outputs to be tied to the X68257 AS, E,
and R/
W
inputs respectively.
The falling edge of AS will latch the addresses for both
a read and write operation. The state of the R/
W
output
determines the operation to be performed, with the E
signal acting as a data strobe.
If R/
W
is HIGH and CE is HIGH (read operation) data will
be output on A/D
0
–A/D
7
after E transitions HIGH. If
R/
W
is LOW and CE is HIGH (write operation) data
present at A/D
0
–A/D
7
will be strobed into the X68257 on
the HIGH to LOW transition of E.
Typical Application
6539 ILL F03.2
31
32
33
34
35
36
37
38
16
15
14
13
12
11
10
9
26
28
27
17
18
19
20
22
21
11
12
12
15
16
17
18
19
25
24
21
23
2
26
1
5
3
27
22
VCC
20
4
X68257
68HC11
U
U
CE
SEL
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
A8
A9
A10
A11
A12
A13
A14
CE
AS
R/W
E
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
AS
R/W
E
PE0
PE1
PE2
PE3
VRH
VRL
XTAL
EXTAL
RESET
IRQ
XIRQ
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
MODA
MODB
PD0
PD1
PD2
PD3
PD4
PD5
30
29
39
41
40
8
7
6
5
4
3
2
1
25
24
42
43
44
45
46
47
MISO
MOSI
SCK
SS