X68C64 SLIC
E
2
2
PIN NAMES
Symbol
Description
AS
A/D
0
–A/D
7
A
8
–A
12
E
R/
W
CE
WC
SEL
V
SS
V
CC
Address Strobe
Address Inputs/Data I/O
Address Inputs
Enable Input
Read/Write Input
Chip Enable
Write Control
Device Select—Connect to V
SS
Ground
Supply Voltage
2134 PGM T01
The X68C64 component is an 8K x 8 E
2
PROM fabri-
cated with advanced CMOS Textured Poly Floating
Gate Technology. The X68C64 features a Multiplexed
Address and Data bus allowing direct interface to a
variety of popular single-chip microcontrollers oper-
ating in expanded multiplexed mode without the need
for additional interface circuitry.
The X68C64 is internally configured as two indepen-
dent 4K x 8 memory arrays. This feature provides the
ability to perform nonvolatile memory updates in one
array and continue operation out of code stored in the
other array; effectively eliminating the need for an
auxiliary memory device for code storage.
To write to the X68C64 SLIC E
2
,
a three-byte com-
mand sequence must precede the byte(s) being writ-
ten. This sequence called Software Data Protection
prevents the loss of data or program information due
to inadvertant write cycles during power-up or power-
down. The X68C64 SLIC E
2
also provides a second
generation software data protection scheme called
Block Protect.
Block Protect can provide write lockout of the entire
device or selected 1K blocks. There are eight 1K x 8
blocks that can be write protected individually in any
combination required by the user. Block Protect, in
additional to Write Control input, allows the different
segments of the memory to have varying degrees of
alterability in normal system operation.
For further information on the X68C64 hardware
interface, consult the X68C64 Data Sheet.
PIN CONFIGURATION
DIP/SOIC
2134 FHD F02
NC
A12
NC
NC
WC
SEL
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
R/W
AS
A8
A9
A11
E
A10
CE
A/D7
A/D6
A/D5
X68C64