X68C64
3
PRINCIPLES OF OPERATION
The X68C64 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The
X68C64 provides 8K bytes of E
2
PROM which can be
used either for Program Storage, Data Storage, or a
combination of both in systems based upon Von
Neumann (68XX) architectures. The X68C64 incorpo-
rates the interface circuitry normally needed to decode
the control signals and demultiplex the Address/Data
bus to provide a “Seamless” interface.
The interface inputs on the X68C64 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip
microcontroller.
The X68C64 is internally organized as two independent
planes of 4K bytes of memory with the A
12
input select-
ing which of the two planes of memory are to be
accessed. While the processor is executing code out of
one plane, write operations can take place in the other
plane, allowing the processor to continue execution of
code out of the X68C64 during a byte or page write to the
device.
The X68C64 also features an advanced implementation
of the Software Data Protection scheme, called Block
Protect, which allows the device to be broken into 8
independent sections of 1K bytes. Each of these sec-
tions can be independently enabled for write operations;
thereby allowing certain sections of the device to be
secured so that updates can only occur in a controlled
environment (e.g. in an automotive application, only at
an authorized service center). The desired set-up con-
figuration is stored in a nonvolatile register, ensuring the
configuration data will be maintained after the device is
powered down.
The X68C64 also features a Write Control input (
WC
),
which serves as an external control over the completion
of a previously initiated page load cycle.
The X68C64 also features the industry standard
E
2
PROM characteristics such a byte or page mode
write and Toggle Bit Polling.
DEVICE OPERATION
Motorola 68XX operation requires the microcontroller’s
AS, E, and R/
W
outputs tied to the X68C64 AS, E, and
R/
W
inputs respectively.
The falling edge of AS will latch the addresses for both
a read and write operation. The state of R/
W
output
determines the operation to be performed, with the E
signal acting as a data strobe.
If R/
W
is HIGH and CE HIGH (read operation), data will
be output on A/D
0
–A/D
7
after E transitions HIGH. If
R/
W
is LOW and CE is HIGH (write operation), data
presented at A/D
0
–A/D
7
will be strobed into the X68C64
on the HIGH to LOW transition of E.
Typical Application
EXTAL
8 MHz
OSC.
V
CC
V
CC
V
SS
24
30
24
12
X68C64
68HC11A8
29
8
25MODA
MODB
XTAL
7
8
9
10
11
13
14
15
21
20
17
19
2
16
5
22
18
23
6
31
32
33
34
35
36
37
38
16
15
14
13
12
9
26
27
28
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
A8
A9
A10
A11
A12
CE
WC
AS
E
R/W
SEL
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PB0
PB1
PB2
PB3
PB4
PB7
AS
E
R/W
3868 ILL F03.2
V
CC