參數(shù)資料
型號: X76F102S8
英文描述: The X76F102 is a Password Access Security Supervisor, containing one 896-bit Secure SerialFlash array
中文描述: 該X76F102是一個密碼訪問安全主管,包含一個896位安全SerialFlash陣列
文件頁數(shù): 9/18頁
文件大小: 103K
代理商: X76F102S8
X76F102
9
AC CHARACTERISTICS
(T
A
= -40C to +85C, V
CC
= +3.0V to +5.5V, unless otherwise specified.)
Notes:
1.
C
b
= total capacitance of one bus line in pF
t
AA
= 1.1μs Max below V
CC
= 3.0V.
2.
RESET AC SPECIFICATIONS
Power Up Timing
Notes:
1.
Delays are measured from the time V
CC
is stable until the specified operation can be initiated. These parameters are periodically sampled
and not 100% tested.
Typical values are for T
A
= 25C and V
CC
= 5.0V
2.
Nonvolatile Write Cycle Timing
Notes:
1.
t
WC
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Symbol
f
SCL
t
AA(2)
Parameter
Min
Max
Units
SCL Clock Frequency
0
1
MHz
SCL LOW to SDA Data Out Valid
0.1
0.9
μ
s
t
BUF
Time the Bus Must Be Free Before a New Transmission Can
Start
1.2
μ
s
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
Start Condition Hold Time
0.6
μ
s
Clock LOW Period
1.2
μ
s
Clock HIGH Period
0.6
μ
s
Start Condition Setup Time (for a Repeated Start Condition)
0.6
μ
s
Data In Hold Time
10
ns
Data In Setup Time
100
ns
t
R
SDA and SCL Rise Time
20+0.1XC
b(1)
20+0.1XC
b(1)
300
ns
t
F
SDA and SCL Fall Time
300
ns
t
SU:STO
t
DH
t
NOL
t
RDV
t
CDV
t
RST
t
SU:RST
Stop Condition Setup Time
0.6
μ
s
Data Out Hold Time
0
μ
s
RST to SCL Non-Overlap
500
ns
RST LOW to SDA Valid During Response to Reset
0
450
ns
CLK LOW to SDA Valid During Response to Reset
0
450
ns
RST High Time
1.5
μ
s
RST Setup Time
500
ns
Symbol
Parameter
Min.
Typ
(2)
Max.
Units
t
PUR(1)
t
PUW(1)
Time from Power Up to Read
1
mS
Time from Power Up to Write
5
mS
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
t
WC(1)
Write Cycle Time
5
10
mS
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