FN8156.0 February 2, 2005 AC Timing Notes: (6) MI in the A.C. timing diagram refers to the minimum incremental change in" />
參數(shù)資料
型號: X90100M8I
廠商: Intersil
文件頁數(shù): 4/7頁
文件大?。?/td> 0K
描述: IC DIGITAL CAPACITOR NV 8-MSOP
標(biāo)準(zhǔn)包裝: 80
類型: 數(shù)字電容器
應(yīng)用: 無線
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 管件
4
FN8156.0
February 2, 2005
AC Timing
Notes: (6) MI in the A.C. timing diagram refers to the minimum incremental change in the CTOTAL output due to a change in the counter value.
(7) tIH + tIL ≥ 4s
Endurance and Data Retention VCC = 5V, TA = 25°C unless otherwise specified
PARAMETER
MIN
UNIT
Minimum endurance
100,000
Data changes per bit
Data retention
100
Years
AC Conditions of Test
Input pulse levels
0V to 3V
Input rise and fall times
10ns
Input reference levels
1.5V
AC Electrical Specifications
VCC = 5V, TA = 25°C unless otherwise specified.
SYMBOL
PARAMETER
MIN
TYP (4)
MAX
UNIT
tCl
CS to INC setup
100
ns
tlD
INC HIGH to U/D change
100
ns
tDI
U/D to INC setup
100
ns
tlL(7)
INC LOW period
1
s
tlH(7)
INC HIGH period
1
s
tlC
INC Inactive to CS inactive
1
s
tCPHNS(5) CS Deselect time (NO STORE)
1
s
tCPHS(5)
CS Deselect time (STORE)
10
ms
tIW
INC to CTOTAL change
1
5
s
tCYC
INC cycle time
4
s
tR, tF(5)
INC input rise and fall time
500
s
tPU(5)
Power up to capacitance stable
5
s
tR VCC(5)
VCC power-up rate
0.2
50
V/ms
tWR(5)
Store cycle
510
ms
CS
INC
U/D
CTOTAL
tCI
tIL
tIH
tCYC
tID
tIW
MI
(6)
tIC
tCPHS
tF
tR
10%
90%
(Store)
tDI
tCPHNS
X90100
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