參數(shù)資料
型號(hào): X9110TV14
廠商: Intersil
文件頁(yè)數(shù): 16/18頁(yè)
文件大小: 0K
描述: IC DCP 100K 1024TP 14TSSOP
標(biāo)準(zhǔn)包裝: 95
系列: XDCP™
接片: 1024
電阻(歐姆): 100k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 4 線 SPI(芯片選擇,設(shè)備位址)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1238 (CN2011-ZH PDF)
7
FN8158.3
February 13, 2008
Write in Process (WIP bit)
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by
a Write In Process bit (WIP). The WIP bit is read with a Read
Status command (See Figure 4).
Power-up and Down Requirements
At all times, the V+ voltage must be greater than or equal to
the voltage at RH or RL, and the voltage at RH or RL must be
greater than or equal to the voltage at V-. During power-up
and power-down, VCC, V+, and V- must reach their final
values within 1msec of each other.
ID3
ID2
ID1
ID0
0
A0
I2
I1
I0
RB
RA
SCK
SI
CS
0101
R/W
DEVICE ID
INTERNAL
INSTRUCTION
OPCODE
ADDRESS
REGISTER
0
ADDRESS
0
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
ID3 ID2 ID1 ID0 0
A0 R/W I2
00
SCK
SI
0
X
X0
0
XX
X
W
C
R
9
W
C
R
8
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
I1
I0 0 RB RA
0
101
0
XX
X
DEVICE ID
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
WIPER
POSITION
0
FIGURE 3. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
ID3 ID2 ID1 ID0 0
A0 R/W I2
00
SCK
SI
1
0
X
X0
0
XX
X
WIP
CS
I1
I0
0 RB RA
01
0
1
0
XX
X
DEVICE ID
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
STATUS
BIT
X X
0
00
0 0
0
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
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