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參數(shù)資料
| 型號： | X9119TV14-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Single Supply/Low Power/1024-Tap/2-Wire Bus |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 131K |
| 代理商： | X9119TV14-2.7 |
X9119 – Preliminary Information
Characteristics subject to change without notice.
5 of 22
REV 1.1.11 3/12/02
www.xicor.com
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry
Register 0
(DR0)
Serial
Bus
Input
Parallel
Bus
Input
Counter
Register
(WCR)
RH
RL
RW
10
10
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then R
W
= R
L
If
WCR = 3FF[HEX]
then
R
W
=
R
H
Wiper
Register 1
(DR1)
Register 2
(DR2)
Register 3
(DR3)
Serial Interface Description
S
ERIAL
I
NTERFACE
The X9119 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9119 will be considered a
slave device in all applications.
C
LOCK
AND
D
ATA
C
ONVENTIONS
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.
S
TART
C
ONDITION
All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9119 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is met.
See Figure 3.
S
TOP
C
ONDITION
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH. See Figure 3.
A
CKNOWLEDGE
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9119 will respond with a final acknowledge.
See Figure 2.
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