參數(shù)資料
型號: X9119TV14IZ-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Single Supply/Low Power/1024-Tap/2-Wire Bus
中文描述: 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO14
封裝: 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-14
文件頁數(shù): 7/23頁
文件大小: 131K
代理商: X9119TV14IZ-2.7
X9119 – Preliminary Information
Characteristics subject to change without notice.
7 of 22
REV 1.1.11 3/12/02
www.xicor.com
Instruction and Register Description
D
EVICE
A
DDRESSING
: I
DENTIFICATION
B
YTE
(ID
AND
A)
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier. The ID[3:0] bits is the device id for the
X9119; this is fixed as 0101[B] (refer to Table 1).
The A2–A0 bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A2–A0 input pins. The slave address is
externally specified by the user. The X9119 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9119 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A2–A0 inputs can
be actively driven by CMOS input signals or tied to V
CC
or V
SS
. The R/W bit is the LSB and is be used to
program the device for read or write operations.
I
NSTRUCTION
B
YTE
AND
R
EGISTER
S
ELECTION
The next byte sent to the X9119 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (IOP[2:0]). The RB and RA bits point to one of
the four registers. The format is shown below in
Table 2.
Table 3 provides a complete summary of the
instruction set opcodes.
Table 1. Identification Byte Format
Table 2. Instruction Byte Format
Register Selected
DR0
DR1
DR2
DR3
RB
0
0
1
1
RA
0
1
0
1
ID3
0
(MSB)
ID2
1
ID1
0
ID0
1
A2
A1
A0
R/W
(LSB)
Device Type
Identifies
Internal Slave
Address
Read or
Write Bit
I2
I1
I0
0
RB
RA
0
0
(MSB)
(LSB)
Instruction
Opcode
Register
Selection
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