參數(shù)資料
型號: X9241AMSI
元件分類: 數(shù)字電位計
英文描述: Quad Digitally Controlled Potentiometer (XDCP)
中文描述: 四重數(shù)控電位器(數(shù)字電位器)
文件頁數(shù): 1/18頁
文件大小: 364K
代理商: X9241AMSI
REV 1.1.13 12/09/02
Characteristics subject to change without notice.
1 of 18
www.xicor.com
X9241A
Quad Digitally Controlled Potentiometer (XDCP
)
FEATURES
Four potentiometers in one package
2-wire serial interface
Register oriented format
—Direct read/write/transfer of wiper positions
—Store as many as four positions per
potentiometer
Terminal Voltages: +5V, -3.0V
Cascade resistor arrays
Low power CMOS
High Reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
16-bytes of nonvolatile memory
3 resistor array values
—2K
to 50K
mask programmable
—Cascadable for values of 500
Resolution: 64 taps each pot
20-lead plastic DIP, 20-lead TSSOP and 20-lead
SOIC packages
to 200K
DESCRIPTION
The X9241A integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
Low Power/2-Wire Serial Bus
BLOCK DIAGRAM
Data
8
R1
R0
R3
R2
V
H0
/R
H0
V
L0
/R
L0
V
W0
/R
W0
Wiper
Counter
Register
(WCR)
V
H1
/R
H1
V
L1
/R
L1
V
W1
/R
W1
Register
Array
Pot 1
Wiper
Counter
Register
(WCR)
R1
R0
R3
R2
SCL
SDA
A0
A1
A2
A3
Interface
and
Control
Circuitry
V
H2
/
R
H2
V
L2
/R
L2
V
W2
/R
W2
V
H3
/R
H3
V
L3
/R
L3
V
W3
/R
W3
Register
Array
Pot 2
Wiper
Counter
Register
(WCR)
R1
R0
R3
R2
Register
Array
Pot 3
Wiper
Counter
Register
(WCR)
R1
R0
R3
R2
V
CC
V
SS
A
PPLICATION
N
OTE
A V A I L A B L E
AN20 AN42–48 AN50-53 AN73 AN99 AN115 AN120 AN124 AN133 AN134 AN135
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